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1/27 ? semiconductor MSM65524A/65p524 general description the MSM65524A is a high-performance 8-bit microcontroller that employs oki original nx-8/ 50 cpu core. with a minimum instruction execution time of 400 ns (10mhz clock), the MSM65524A is capable of high-speed processing, and includes 16k bytes of program memory, 384 bytes of data memory, timers, serial ports, an a/d converter and pwms on chip. also available are the msm65p524, which replaces the on-chip program memory with one-time prom, and the msm65x524a, which uses the external program memory. features ? operating range operating frequency : 0 to 10mhz (v dd =4.5 to 5.5v) 0 to 5mhz (v dd =2.7 to 5.5v) operating voltage : 2.7 to 5.5v operating temperature : C40 to +85 c ? memory space : 64k bytes internal program memory : 16k bytes internal data memory : 384 bytes ? minimum instruction execution time : 400ns @ 10 mhz ? powerful instruction set : 83 basic instructions 8/16-bit operation instructions bit manipulation instructions compound function instructions ? abundant addressing modes ? multiplication/division operation functions : 8 8 ? 16 16 ? 8 ? 16 ... 8 ? i/o port input-output port : 5 ports 8 bits 1 port 4 bits input port : 1 port 8 bits ? timers : 8-bit auto-reload timer 2 16-bit auto-reload timer 1 watchdog timer 1 ? counters : time base counter 1 16-bit free-running counter 1 ? capture input : 1 channel ? compare output : 2 channels ? serial ports : shift register 1 serial port with baud rate generator (uart/synchronous) 1 ? a/d converter : 8 bits 8 channels ? pwm : 8 bits 2 channels pwm with auto-reload timer for period setting ? semiconductor MSM65524A/65p524 8-bit microcontroller with a/d converter e2e1016-27-y6 this version: jan. 1998 previous version: nov. 1996
2/27 ? semiconductor MSM65524A/65p524 ? external interrupts : 3 ? interrupt sources : 19 ? package options 64-pin plastic shrink dip (sdip64-p-750-1.78) : (product name: MSM65524A- ss, msm65p524- ss) 64-pin plastic qfp (qfp64-p-1414-0.80-bk) : (product name: MSM65524A- gs-bk, msm65p524- gs-bk) 68-pin plastic qfj (plcc) (qfj68-p-s950-1.27): (product name: MSM65524A- js, msm65p524- js) indicates the code number.
3/27 ? semiconductor MSM65524A/65p524 block diagram osc 0 osc 1 reset hstop * v dd gnd osc cont. rom (16k bytes) ext.mem. cont. cpu core inst. dec. t/c ir alu gmar pc ar br psw sp lmar bus cont. i/o port ram (384 bytes) tbc wdt 16-bit timer 16-bit frc cap 1, cmp 2 sio ad0-7* a8-15* rd wr * ale ea t2ck* gate* cap* cmp0* cmp1* txd* rxd* p2 p3 p4 p5 * secondary functions of ports 8 8 8 8 8 8-bit timer 4** t1out* t0ck* 8-bit shift-reg. interrupt cont. sfto* sfti* sftck* int0* int1* int2* mul/div p1 p0 p6 8-bit pwm 2 pwm0* pwm1* 8-bit a/d c 8ch ** one timer doubles as the sio baud rate generator, another doubles as a pwm clock source. av dd v rh v rl agnd ai0*- ai7*
4/27 ? semiconductor MSM65524A/65p524 pin configuration (top view) 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p3.7/sftck p5.0/pwm0 p5.1/pwm1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 p3.0/t2ck p3.1/cap p3.2/cmp0 p3.3/cmp1 p3.4/int2 p3.5/sfto p3.6/sfti p0.6/ad6 v dd av dd v rh v rl p6.7/ai7 p6.6/ai6 p6.5/ai5 p6.4/ai4 p6.3/ai3 p6.2/ai2 p6.1/ai1 p6.0/ai0 agnd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 45 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 21 22 23 24 25 26 27 28 29 30 31 32 44 43 42 41 40 39 38 37 36 35 34 33 reset p0.7/ad7 p2.0/rxd ea p2.1/txd ale p2.2/int0 rd p2.3/int1/gate p1.7/a15 p2.4/t0ck p1.6/a14 p2.5/ hstop p1.5/a13 p2.6/ wr p1.4/a12 p2.7/t1out p1.3/a11 osc1 p1.2/a10 osc0 p1.1/a9 gnd p1.0/a8 64-pin plastic shrink dip
5/27 ? semiconductor MSM65524A/65p524 pin configuration (top view) (continued) 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 p4.4 p4.5 p4.6 p4.7 p3.0/t2ck p3.1/cap p3.2/cmp0 p3.3/cmp1 p3.4/int2 p3.5/sfto p3.6/sfti p6.3/ai3 p6.2/ai2 p6.1/ai1 p6.0/ai0 agnd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 64 63 62 61 60 59 58 57 56 55 54 p4.3 p4.2 p4.1 p4.0 p5.3 p5.2 p5.1/pwm1 p5.0/pwm0 v dd av dd v rh 17 18 19 20 21 22 23 24 25 26 27 p2.3/int1/gate p2.4/t0ck p2.5/ hstop p2.6/ wr p2.7/t1out osc1 osc0 gnd p1.0/a8 p1.1/a9 p1.2/a10 12 p3.7/sftck 13 reset 14 p2.0/rxd 15 p2.1/txd 16 p2.2/int0 28 p1.3/a11 29 p1.4/a12 30 p1.5/a13 31 p1.6/a14 32 p1.7/a15 37 p0.6/ad6 36 p0.7/ad7 35 ea 34 ale 33 rd 53 v rl 52 p6.7/ai7 54 p6.6/ai6 50 p6.5/ai5 49 p6.4/ai4 64-pin plastic qfp
6/27 ? semiconductor MSM65524A/65p524 pin configuration (top view) (continued) p6.4/ai4 p6.5/ai5 p6.6/ai6 p6.7/ai7 v rl v rh av dd v dd p5.0/pwm0 p5.1/pwm1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 p1.7/a15 p1.6/a14 p1.5/a13 p1.4/a12 p1.3/a11 p1.2/a10 p1.1/a9 p1.0/a8 gnd osc0 osc1 p2.7/t1out p2.6/ wr p2.5/ hstop p2.4/t0ck p2.3/int1/gate p4.4 p4.5 p4.6 p4.7 p3.0/t2ck p3.1/cap p3.2/cmp0 p3.3/cmp1 p3.4/int2 p3.5/sfto p3.6/sfti p3.7/sftck reset p2.0/rxd p2.1/txd p2.2/int0 p6.3/ai3 p6.2/ai2 p6.1/ai1 p6.0/ai0 agnd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea ale rd nc nc nc nc 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 nc: no-connection pin 68-pin plastic qfj (plcc)
7/27 ? semiconductor MSM65524A/65p524 pin description basic functions function symbol type description power supply v dd +5v digital power supply gnd 0v digital ground osc0 system clock input pin. quartz oscillator or ceramic oscillator is connected between osc0 and osc1 . for external clock, input at osc0, leaving osc1 open. osc1 system clock output pin i o reset system reset input (program starts from address 0040h); internal pull-up resistance i ea program memory select input pin. "l" level input for external program memory; "h" level input for internal program memory. i rd read strobe signal during external memory access o ale address latch signal during external memory access o port 0 8-bit input-output port during external memory access, becomes address/data bus for address output, instruction fetch or data read/write along with ale, rd and wr pins. i/o port 1 8-bit input-output port address bus during external memory access i/o port 2 port 3 port 4 8-bit input-output port 3. secondary functions shown in following table are added for ports 2 and 3. i/o oscillation control port port 6 8-bit input port functions as analog input channel during a/d conversion. i av dd agnd v rh v rl +5v analog power supply 0v analog ground +5v analog reference voltage 0v analog reference voltage port 5 4-bit input-output port secondary functions shown in following table are added for port 5. i/o
8/27 ? semiconductor MSM65524A/65p524 secondary functions symbol type description int0 p2.2 secondary function external interrupt 0 input pin. i int1/gate p2.3 secondary functions external interrupt 1 input pin. also used as input pin for gate signal for timer 0 count enable/disable. i t0ck p2.4 secondary function timer 0 external clock input pin. i hstop p2.5 secondary function hard stop mode input pin; stops system clock oscillation with "l" level input. i wr p2.6 secondary function write strobe signal output pin during external data memory access. o t1out p2.7 secondary function output pin for signal that 2-divided timer 1 overflow. o sfto p3.5 secondary function shift register data output pin. o sfti p3.6 secondary function shift register data input pin. i sftck p3.7 secondary function shift register synchronizing clock input/output pin. i/o rxd p2.0 secondary function uart: input pin for serial port receive data. synchronous: input/output pin for serial port transmit/receive data. i/o txd p2.1 secondary function uart: output pin for serial port transmit data. synchronous: output pin for serial port synchronizing clock. o t2ck p3.0 secondary function timer 2 external clock input pin. i cap p3.1 secondary function capture trigger input pin. i cmp0 p3.2 secondary function compare output channel 0 output pin. o cmp1 p3.3 secondary function compare output channel 1 output pin. o int2 p3.4 secondary function external interrupt 2 input signal. i pwm0 p5.0 secondary function pwm channel 0 output pin. o pwm1 p5.1 secondary function pwm channel 1 output pin. o
9/27 ? semiconductor MSM65524A/65p524 port circuit configuration type port electrical characteristics (v dd =5v) p0.0/ad0 to p0.7/ad7 1 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v "h" output voltage: ? v oh =3.75v ? i oh =C400 m a "l" output voltage: ? v ol =0.4v ? i ol =3.2ma circuit configuration p1.0/a8 to p1.7/a15 2 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v "h" output voltage: ? v oh =3.75v ? i oh =C200 m a "l" output voltage: ? v ol =0.4v ? i ol =1.6ma p0d p0 dir data bus external memory control port0 p1d p1 dir data bus external memory control port1 data bus pxd px dir secondary output function (x=2 to 5) px mod portx secondary input function 3 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v p2.6/ wr "h" output voltage: ? v oh =3.75v ? i oh =C400 m a "l" output voltage: ? v ol =0.4v ? i ol =3.2ma ports other than p2.6/ wr "h" output voltage: ? v oh =3.75v ? i oh =C200 m a "l" output voltage: ? v ol =0.4v ? i ol =1.6ma p2.0/rxd, p2.1/txd, p2.6/ wr , p2.7/t1out, p3.2/cmp0, p3.3/cmp1, p3.5/sfto, p3.7/sftck, p5.0/pwm0, p5.1/pmw1
10/27 ? semiconductor MSM65524A/65p524 pxd px dir data bus (x=2 to 5) portx secondary input function type port electrical characteristics (v dd =5v) 4 "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v "h" output voltage: ? v oh =3.75v ? i oh =C200 m a "l" output voltage: ? v ol =0.4v ? i ol =1.6ma circuit configuration p2.2/int0, p2.3/int1/gate, p2.4/t0ck, p2.5/ hstop , p3.0/t2ck, p3.1/cap, p3.4/int2, p3.6/sfti, p4.0 to p4.7, p5.2 to p5.3 5 p6.0/ai0 to p6.7/ai7 port6 data bus "h" input voltage: ? v ih =2.4v "l" input voltage: ? v il =0.8v to a/d converter port circuit configuration (continued)
11/27 ? semiconductor MSM65524A/65p524 100h 80h 40h 30h 20h 10h 0 0ffffh 4000h 100h 80h 40h 20h internal memory local memory space sfr data memory local register set 3 local register set 2 local register set 1 local register set 0 general memory space external memory program memory vector call table area program memory interrupt vector table area vector call table area 0 1ffh data memory page 1 page 0 memory maps
12/27 ? semiconductor MSM65524A/65p524 absolute maximum ratings parameter unit supply voltage v dd =av dd C0.3 to 7.0 symbol condition rating ta=25c input voltage v i C0.3 to v dd +0.3 output voltage v o C0.3 to v dd +0.3 power dissipation p d 400 ta=25c per package storage temperature t stg C55 to +150 v mw c gnd=agnd=0v analog reference voltage analog input voltage v rh , v rl v ai C0.3 to v dd +0.3 C0.3 to v dd +0.3 recommended operating conditions parameter unit supply voltage v dd 2.7 to 5.5 symbol condition range refer to figure 1. memory hold voltage v ddmh 2.0 to 5.5 f osc =0 hz operating frequency * 1 f osc 1 to 10 refer to figure 1. external clock operating frequency f extclk 0 to 10 refer to figure 1. operating temperature t op C40 to +85 v mhz mhz c analog supply voltage av dd 2.7 to 5.5 analog reference voltage v rh 2.7 to 5.5 analog input voltage v ai 0 to v dd v dd =av dd =v rh gnd=agnd=v rl =0v *1 this is due to the standard of a crystal oscillator or resonator. figure 1. power supply voltage vs. operating frequency 2 5 4 6 8 10 23456 1 5.5 ta=C40 to +85c f osc , f extclk (mhz) oscillator frequency > 1mhz v dd (v) 2.7
13/27 ? semiconductor MSM65524A/65p524 electrical characteristics dc characteristics 1 (v dd =4.5 to 5.5v) (gnd=0v, ta=C40 to +85c) parameter symbol condition min. typ. max. unit "h" input voltage 1 v ih1 2.4 v dd +0.3 "h" input voltage 2 v ih2 0.7v dd v dd +0.3 "l" input voltage v il C0.3 0.8 "h" output voltage 1 v oh1 i oh =C200 m a 0.75v dd "h" output voltage 2 v oh2 i oh =C400 m a 0.75v dd "l" output voltage 1 v ol1 i ol =1.6ma 0.4 "l" output voltage 2 v ol2 i ol =3.2ma 0.4 input leakage current 1 i li1 v i =v dd /0v 1 input leakage current 2 i li2 v i =v dd /0v 10 "l" input current i il C40 C120 C400 input capacitance c i f=1mhz, ta=25c 5 static current consumption i dds 5v, stop mode *8 50 dynamic current consumption i dd 10mhz, 5v, no load refer to figure2 2040 v m a pf m a ma v i =0v *1 *2 *3 *4 *3 *4 *5 *6 *7 *1 excluding osc0 and reset *2 osc0 and reset *3 excluding p0, ale, rd , p2.6/ wr *4 p0, ale, rd , p2.6/ wr *5 ea , p6 *6 excluding reset , ea , p6 *7 reset *8 the ports set for input mode are v dd or 0v and the ports except these are no load.
14/27 ? semiconductor MSM65524A/65p524 *1 excluding osc0 and reset *2 osc0 and reset *3 excluding p0, ale, rd , p2.6/ wr *4 p0, ale, rd , p2.6/ wr *5 ea , p6 *6 excluding reset , ea, p6 *7 reset *8 the ports set for input mode are v dd or 0v and the ports except these are no load. (gnd=0v, ta=C40 to +85c) parameter symbol condition min. typ. max. unit "h" input voltage 1 v ih1 0.5v dd +0.2 v dd +0.3 "h" input voltage 2 v ih2 0.6v dd +0.4 v dd +0.3 "l" input voltage v il C0.3 0.15v dd +0.1 "h" output voltage 1 v oh1 i oh =C10 m a 0.75v dd "h" output voltage 2 v oh2 i oh =C20 m a 0.75v dd "l" output voltage 1 v ol1 i ol =10 m a 0.1 "l" output voltage 2 v ol2 i ol =20 m a 0.1 input leakage current 1 i li1 v i =v dd /0v 1 input leakage current 2 i li2 v i =v dd /0v 10 "l" input current i il v dd =2.7 to 3.3v C40 C120 C240 input capacitance c i f=1mhz, ta=25c 5 static current consumption i dds 3v, stop mode *8 25 dynamic current consumption i dd 5mhz, 3v, no load refer to figure 2 615 v m a pf m a ma v i =0v *1 *2 *3 *4 *3 *4 *5 *6 *7 dc characteristics 2 (2.7 v dd <4.5v)
15/27 ? semiconductor MSM65524A/65p524 10 20 30 40 50 23456 i dd (ma) v dd (v) 10 20 30 40 50 23456 i dd (ma) v dd (v) 10 20 30 40 50 23456 i dd (ma) v dd (v) 10mhz max. typ. max. typ. max. typ. 6mhz 2mhz ta=C40 to +85c, no load figure 2. voltage vs. current
16/27 ? semiconductor MSM65524A/65p524 ac characteristics ? external memory control (v dd =av dd =v rh =2.7 to 5.5v, gnd=agnd=v rl =0v, ta=C40 to +85c) parameter symbol condition min. max. unit clock period t c 100 "l" clock pulse width t clw 45 "h" clock pulse width t chw c l =100pf 45 ale pulse width t aw t c +t chw C20 ale pulse delay time 1 t ald1 t clw C20 ale pulse delay time 2 t ald2 t clw C20 rd pulse width t rw t c +t chw C20 rd pulse delay time t rd t clw C20 t clw +20 wr pulse width t ww t c +t chw C40 wr pulse delay time t wd t clw C20 t clw +40 "l" address setup time t las t c C40 "h" address setup time t has t c C40 "l" address hold time t lah t clw C20 bus float time t laz 20 "h" address hold time t hahr t c C20 "h" address hold time t hahw t c C20 read data access time t rdaa t c +t clw C15 read data access time t rdar t chw +10 read data hold time t rdh 0 write data setup time t wds t c +t chw C40 write data hold time t wdh t clw C20 v dd =4.5 to 5.5v clock period t c 200 "l" clock pulse width t clw 90 "h" clock pulse width t chw 90 v dd =2.7 to 5.5v ns
17/27 ? semiconductor MSM65524A/65p524 osc0 t chw t c t aw t clw t rd t rdar t las t laz t rdaa t has t wd t wds t hahw t rw t ald1 t lah t rdh t hahr t ww t ald2 t wdh address l inst or data in address h address l data out address h ale rd p0 p1 wr p0 p1
18/27 ? semiconductor MSM65524A/65p524 ? cpu control (v dd =av dd =v rh =2.7 to 5.5v, gnd=agnd=v rl =0v, ta=C40 to +85c) parameter symbol condition min. max. unit reset pulse width *1 t resw1 20 ns reset pulse width *2 t resw2 *3 *1 excluding power on, stop mode and hard stop mode. *2 in power on, stop mode and hard stop mode. *3 oscillation stabilization time depends on resonator. reset pulse width t resw1, 2 reset ? peripheral control 1 (v dd =av dd =v rh =2.7 to 5.5v, gnd=agnd=v rl =0v, ta=C40 to +85c) parameter symbol condition min. max. unit clock period t c 100 ns external interrupt pulse width t exiw 4 t c external clock pulse width t t0cw 4 t c gate pulse width t t0gw 1 t toclk *1 osc exi t0 external clock pulse width t t2cw 4 t c t2 cap pulse width t capw 12 t c cap v dd =4.5 to 5.5v v dd =2.7 to 5.5v 200 *1 t t0clk : timer 0 count clock period selected by t0con.
19/27 ? semiconductor MSM65524A/65p524 1) exi pulse width 2) t0 3) t2 4) cap osc0 t c t clw int0-2 t exiw t0ck t t0cw gate t t0gw t2ck t t2cw cap t capw
20/27 ? semiconductor MSM65524A/65p524 (v dd =av dd =v rh =2.7~5.5v, gnd=agnd=v rl =0v, ta=C40 to +85c) parameter symbol condition min. max. unit clock period t c 100 ns sftck period t sfc 8 t c sftck "l" pulse width t sfclw 4 t c C20 sftck "h" pulse width t sfchw 4 t c C20 osc sft sftck setup time t sfos t sfclw C100 sfto hold time t sfoh t sfchw C100 sfti setup time t sfis 100 sfti hold time t sfih 100 c l =100pf synchronous clock period t sic 8 t c synchronous clock "l" pulse width t siclw 4 t c C20 synchronous clock "h" pulse width t sichw 4 t c C20 output data setup time t sios 6 t c C100 output data hold time t sioh 2 t c C100 input data setup time t siis t c +t clw +100 input data hold time t siih 0 sio (clock synchro- nous mode) v dd =4.5 to 5.5v 200 v dd =2.7 to 5.5v ? peripheral control 2
21/27 ? semiconductor MSM65524A/65p524 t sfclw t sfchw t sfc t sfos t sfoh t sfis t sfih sftck sfto sfti 1) sft 2) sio (clock synchronous mode) t siclw t sichw t sic t sios t sioh t siis t siih txd rxd (transmission) rxd (reception)
22/27 ? semiconductor MSM65524A/65p524 a/d converter characteristics 1 * the transition time after the g0 bit goes to "1" is 14.8 m s/ch. (v dd =av dd =v rh =5v10%, gnd=agnd=v rl =0v, ta=-40 to +85c) parameter symbol condition min. max. unit resolution n bit absolute error e l +1.5 differential linearity error e d 0.5 zero point error e zs +1.5 full scale error e fs C1.5 crosstalk e ct 0.5 analog input source impedance r i 5k w typ. 8 conversion time * t conv 16 C1.5 see the recommended circuit (fig. 3). see the measuring circuit (fig. 4). f osc =10 mhz lsb lsb lsb lsb lsb m s/ch a/d converter characteristics 2 * the transition time after the g0 bit goes to "1" is 29.6 m s/ch. (v dd =av dd =v rh =2.7 to 4.5v, gnd=agnd=v rl =0v, ta=-40 to +85c) parameter symbol condition min. max. unit resolution n bit absolute error e l +2 differential linearity error e d 1 zero point error e zs +2 full scale error e fs C2 crosstalk e ct 1 analog input source impedance r i 5k w typ. 8 conversion time * t conv 32 C2 see the recommended circuit (fig. 3). see the measuring circuit (fig. 4). f osc =5 mhz lsb lsb lsb lsb lsb m s/ch
23/27 ? semiconductor MSM65524A/65p524 ? definitions of terms (1) resolution the minimum distinguishable analog value. for 8 bits, 2 8 =256, i.e. (v rh Cv rl ) ? 256. (2) linearity error the variance between the ideal conversion characteristics as an 8-bit a/d converter and actual conversion characteristics (does not include quantatized error). the ideal conversion characteristics refer to steps of the voltage between v rh and v rl into 256 intervals. (3) differential linearity error indicates the smoothness of the conversion. the width of analog input voltage corresponding to the change by one bit of digital output is 1 lsb = (v rh -v rl ) ? 256 ideally. the variance between this ideal bit size and bit size at arbitrary point in the conversion range. (4) zero scale error the variance between the ideal conversion characteristics at the switching point of digital output "000h to 001h" and actual conversion characteristics. (5) full scale error the variance between the ideal conversion characteristics at the switching point of digital output "0feh to 0ffh" and actual conversion characteristics.
24/27 ? semiconductor MSM65524A/65p524 figure 3. recommended circuit figure 4. crosstalk measuring circuit C + r 1 analog voltage input 0.1 m f 0.1 m f 0.1 m f 47 m f + +5v 0v av dd v rh ai0-7 v dd v rl agnd gnd MSM65524A r i (analog input source impedance) 5k w C + analog voltage input 0.1 m f 5k w ai0 ai1 ai7 v ref or agnd crosstalk is defined as the difference of a/d conversion result between supplying the same voltage to ai0 to ai7 and supplying voltage shown in this diagram.
25/27 ? semiconductor MSM65524A/65p524 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). sdip64-p-750-1.78 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 8.70 typ.
26/27 ? semiconductor MSM65524A/65p524 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp64-p-1414-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.87 typ. mirror finish
27/27 ? semiconductor MSM65524A/65p524 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj68-p-s950-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 4.50 typ. mirror finish

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